The present invention relates to a D-class amplifier in an integrated circuit, more particularly to a PWM (pulse width modulation)-based D-class amplifier suitable for an inductive load, such as a coil.
D-class amplifiers, which achieve power amplification through pulse width modulation on an input signal, are used for various applications, such as audio amplifiers and motor control drivers, in which further power consumption reduction is desired compared to linear amplifiers. An exemplary D-class amplifier is disclosed in Japanese Patent Application Publication No. 2009-027540 A and the corresponding U.S. patent application Ser. No. 12/219,349 (published as U.S. Patent Application Publication No. 2009/0021305 A), the disclosures of which are incorporated herein by reference.
In the following, a description is given of an issue found by the inventor, with reference to the attached drawings.
In general, a D-class amplifier includes a triangular wave generator 54, a comparator 56 and a bridge circuit 24 as shown in FIG. 1. The comparator 56 compares the input voltage with the level of the triangular wave signal outputted from the triangular wave generator 54 and outputs a pulse wave signal with a duty ratio of [input voltage]/[triangular wave amplitude]. The D-class amplifier achieves power amplification of the input signal by feeding the pulse wave signal to the bridge circuit 24, which incorporates low output impedance switch elements, to switch the power supply voltage. Although the output voltage of a D-class amplifier originally has a pulse waveform, the current is smoothed when the load is inductive. The D-class amplifier can reduce the self power consumption compared to linear amplifiers, since the circuit stage which drives the load performs a switching operation with a low impedance. As shown in FIG. 2, however, such circuit configuration leads to variations in the amplitude of the output pulse voltage when the power supply voltage of the bridge circuit varies. In order to address this, an approach is sometimes used in which the output pulse voltage is fed back through an LPF (low pass filter), as shown in FIG. 3 In the configuration shown in FIG. 3, the LPF includes a resistor R, a capacitor C and an amplifier 58. This configuration provides feed-back of the voltage including information of the power supply voltage, and thereby effectively reduces the error caused by variations in the power supply voltage of the D-class amplifier. The approach in which the output voltage is fed back, however, is not suitable for circuit integration, since a high-order filter circuit is needed for smoothing the output pulse signal. When the PWM frequency is 500 kHz, the amplitude of the triangular wave signal is Vp-p, the power supply voltage of the D-class amplifier is 5 V, and the signal frequency band of the D-class amplifier is 20 kHz, for example, then the voltage obtained by filtering the output pulse signal may exhibit a large error, unless the signal obtained by filtering the output pulse signal has a sufficiently small amplitude compared to the triangular wave amplitude of Vp-p as shown in FIG. 4. In order to achieve an attenuation down to 1% of Vp-p, an attenuation of 54 dB (=1/5/100) is required at the frequency of 500 kHz. On the other hand, the attenuation should be reduced as much as possible in a band lower than 20 kHz, which is the signal band. Accordingly, the filter of the output pulse needs to be structured as an LPF of an order of three or higher, as shown in FIG. 5. This undesirably results in an increase in the circuit size in the actual integration.
As disclosed in Japanese Patent Application Publication No. 2004-088431 A, the output error caused by variations in the power supply voltage of a D-class amplifier can be reduced by feeding back the power supply voltage. This approach, in which the power supply voltage is measured by an A-D converter and fed back, requires high specifications for the A-D converter, including performances of a sampling speed of 300k samples per second and 10-bit resolution (for an error of 0.1%). This undesirably leads to an increase in the circuit size, even when a successive approximation type A-D converter, which has a relatively small size, is used. In the above-mentioned patent document, an approach is proposed for reducing the requirements of the A-D converter. In this approach, as shown in FIG. 6, an A-D converter circuitry includes a HPF (high pass filter) 70, a high-speed A-D converter 71, an LPF (low pass filter) 72, a low-speed A-D converter 73 and an adder 74. The HPF 70 and the high-speed A-D converter 71 are connected in series and the LPF 72 and the low speed A-D converter 73 are also connected in series. The adder 74 adds the outputs of the high-speed and low-speed A-D converters 71 and 73. This configuration, however, requires two filters and two A-D converters, resulting in an increase in the circuit size. In addition, A-D converters usually require anti-aliasing filters on the input and output, although this is not explicitly described in the above-mentioned patent document. When there is no anti-aliasing filter and noise of a frequency higher than a half of the sampling frequency (fs) is superposed on the power supply voltage, this causes aliasing and generates noise of low frequency components, as shown in FIGS. 7A and 7B. FIG. 7A shows the spectrum of an input signal having a uniform distribution in a band between fs/2 and fs and FIG. 7B shows the spectrum of a signal obtained by sampling the input signal at the sampling frequency of fs. Under such situations, the noise and signal components cannot be distinguished and the noise components cannot be removed by providing any sort of filter to the output.